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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MCF52277 Rev. 6, 07/2008
MCF52277
LQFP-176 24 mm x 24 mm MAPBGA-196 15mm x 15mm
MCF5227x ColdFire(R) Microprocessor Data Sheet
Features * Version 2 ColdFire(R) Core with EMAC * Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz * 8 Kbytes configurable cache (instruction only, data only, or split instruction/data) * 128 Kbytes internal SRAM * Support for booting from SPI-compatible flash, EEPROM, and FRAM devices * Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters * 16 channel DMA controller * 16- or 32-bit SDR/DDR controller * USB 2.0 On-the-Go controller * Liquid crystal display controller with support up to 800 x 600 pixels * ADC and touchscreen controller * FlexCAN module * 4 32-bit timers with DMA support * DMA supported serial peripheral interface (DSPI) * 3 UARTs * I2C bus interface * Synchronous serial interface (SSI) * Plus-width modulator (PWM) * Real-time clock (RTC) * Two programmable interrupt controllers (PIT)
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary--Subject to Change Without Notice
Table of Contents
1 2 3 MCF5227x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 ADC Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.4 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6 3.4.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .6 3.4.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6 3.5 Power Consumption Specifications. . . . . . . . . . . . . . . . .6 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .7 4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.2 Pinout--176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3 Pinout--196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .13 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .16 5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .17 ASP Electrical Characteristics . . . . . . . . . . . . . . . . . . . 5.6.1 Gain Calculations . . . . . . . . . . . . . . . . . . . . . . . 5.7 External Interface Timing Specifications . . . . . . . . . . . 5.7.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 5.9 Reset and Configuration Override Timing . . . . . . . . . . 5.10 LCD Controller Timing Specifications . . . . . . . . . . . . . 5.11 USB On-The-Go Specifications. . . . . . . . . . . . . . . . . . 5.12 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 5.13 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 5.14 DMA Timer Timing Specifications . . . . . . . . . . . . . . . . 5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 5.16 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 5.17 JTAG and Boundary Scan Timing Specifications . . . . 5.18 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 18 19 19 19 21 27 27 28 31 32 34 36 36 37 38 40 41 41 41
4
5
6 7 8
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCF52277
JTAG 8K Configurable Cache Version 2 ColdFire Core PLL Serial Boot Facility Oscillator
BDM
128K SRAM
Hardware Divide
EMAC
USB OTG
LCD Controller
eDMA
Crossbar Switch (XBS)
Peripheral Bridge FlexBus Touch Screen SSI DSPI FlexCAN I2C RTC GPIO
SDRAM Controller
EPORT
INTC
2 PITs
3 UARTs
4 DMA Timers
PWM
LEGEND
BDM DSPI eDMA EMAC EPORT GPIO I2 C INTC JTAG - Background debug module - DMA serial peripheral interface - Enhanced direct memory access - Enchance multiply-accumulate unit - Edge port module - General Purpose Input/Output Module - Inter-Intergrated Circuit - Interrupt controller - Joint Test Action Group interface LCD PIT PLL PWM RTC SSI UART USB OTG - Liquid-crystal display - Programmable interrupt timer - Phase locked loop module - Pulse-width modulator - Real time clock - Synchronous Serial Interface - Universal asynchronous receiver/transmitter - Universal Serial Bus On-the-Go controller
Figure 1. MCF52277 Block Diagram
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
MCF5227x Family Comparison
1
MCF5227x Family Comparison
Table 1. MCF5227x Family Configurations
Module ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock / 2) Performance (Dhrystone/2.1 MIPS) Static RAM (SRAM) Configurable Cache ASP Touchscreen Controller LCD Controller USB 2.0 On-the-Go FlexBus External Interface SDR/DDR SDRAM Controller FlexCAN 2.0B communication module Real Time Clock Watchdog Timer 16-channel Direct Memory Access (DMA) Interrupt Controllers (INTC) Synchronous Serial Interface (SSI) I
2C
The following table compares the various device derivatives available within the MCF5227x family.
MCF52274 * up to 120 MHz up to 60 MHz up to 114
MCF52277 * up to 166.67 MHz up to 83.33 MHz up to 159
128 Kbytes 8 Kbytes * 12-bit color * * * * * * * 1 * * * 3 4 2 * * * * 176 LQFP * 18-bit color * * * * * * * 1 * * * 3 4 2 * * * * 196 MAPBGA
DSPI UARTs 32-bit DMA Timers Periodic Interrupt Timers (PIT) PWM Module Edge Port Module (EPORT) General Purpose I/O Module (GPIO) JTAG - IEEE 1149.1 Test Access Port Package
(R)
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part Number MCF52274CLU120 MCF52277CVM160 Description MCF52274 RISC Microprocessor MCF52277 RISC Microprocessor Package 176 LQFP 196 MAPBGA Speed 120 MHz 166.67 MHz Temperature -40 to +85 C -40 to +85 C
3
3.1
Hardware Design Considerations
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible.
10 Board IVDD 10 F 0.1 F PLL VDD Pin
GND
Figure 2. System PLL VDD Power Filter
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be connected between the board EVDD and the USBVDD pin. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible.
0 Board EVDD 10 F 0.1 F USB VDD Pin
GND
Figure 3. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5
Hardware Design Considerations
3.3
ADC Power Filtering
To minimize noise, an external filters is required for the ADCVDD power pin. The filter shown in Figure 4 should be connected between the board EVDD and the ADCVDD pin. The resistor and capacitors should be placed as close to the dedicated ADCVDD pin as possible.
0 Board EVDD 10 F 0.1 F ADC VDD Pin
GND
Figure 4. ADC VDD Power Filter
3.4
Supply Voltage Sequencing
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
3.4.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on the internal ESD protection clamp diodes.
3.4.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. 2. Drop IVDD/PLLVDD to 0 V. Drop EVDD/SDVDD supplies.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Hardware Design Considerations
3.5
Power Consumption Specifications
Table 3. MCF52277 Application Power Consumption1
All application power consumption data is lab data measured on an M52277EVB running the Freescale Linux BSP.
Core Freq. IVDD EVDD 160 MHz SDVDD Total Power
1
Idle (LCD image) 61.4 28.87 18.8 221.211
Idle (audio image) 59.2 25.73 18.57 207.135
Button Demo 84.7 35.3 21.8 282.78
Slideshow Demo 96.5 34.6 23.9 301.95
MP3 Playback 89.2 33.46 22.66 285.006
USB FS File Copy 89.5 29.86 22.2 272.748
Units
mA
mW
All voltage rails at nominal values: IVDD = 1.5 V, EVDD = 3.3 V, and SDVDD = 1.8 V.
350 300 250 200 150 100 50 0 Idle (LCD image) Idle (Audio Image) Button Demo Slideshow Demo MP3 Playback USB FS File Copy
Total Power (mW)
Figure 5. Power Consumption in Various Applications All current consumption data is lab data measured on a single device using an evaluation board. Table 4 shows the typical power consumption in low-power modes. These current measurements are taken after executing a STOP instruction. Table 4. Current Consumption in Low-Power Modes1,2
System Frequency Mode Voltage Supply 80MHz IVDD (mA) Power (mW) WAIT IVDD (mA) Power (mW) 75.1 112.65 61.9 92.85 64MHz 62.7 94.05 52.8 79.20 48MHz 49.2 73.80 42.0 63.00 32MHz 36.6 54.90 31.7 47.55 4MHz (LIMP mode) 3.5 5.25 2.9 4.35
RUN
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Hardware Design Considerations
Table 4. Current Consumption in Low-Power Modes1,2 (continued)
System Frequency Mode Voltage Supply 80MHz IVDD (mA) Power (mW) STOP 0 IVDD (mA) Power (mW) STOP 1 IVDD (mA) Power (mW) STOP 2 IVDD (mA) Power (mW) STOP 3
1
64MHz 48.8 73.20 15.1 22.65 14.9 22.35 1.8 2.70 0.5 0.75
48MHz 38.9 58.35 13.4 20.10 13.2 19.80 1.8 2.70 0.5 0.75
32MHz 29.7 44.55 12.5 18.75 12.4 18.60 1.8 2.70 0.5 0.75
4MHz (LIMP mode) 2.7 4.05 1.3 1.95 1.3 1.95 1.3 1.95 0.5 0.75
57.0 85.50 16.1 24.15 15.9 23.85 1.8 2.70 0.5 0.75
DOZE
IVDD (mA) Power (mW)
All values are measured on an M52277EVB with nominal core voltage(IVDD = 1.5 V). Tests performed at room temperature. All peripheral clocks on prior to entering low-power mode 2 Refer to the Power Management chapter in the MCF52277 Reference Manual for more information on low-power modes.
120 100 RUN 80 60 40 20 0 80 64 48 32 4 (LIMP) System Frequency (MHz) WAIT DOZE STOP 0 STOP 1 STOP 2 STOP 3
IVDD Power Consumption (mW)
Figure 6. IVDD Power Consumption in Low-Power Modes
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
4
4.1
Pin Assignments and Reset States
Signal Multiplexing
The following table lists all the MCF5227x pins grouped by function. The direction column is the direction for the primary function of the pin only. Refer to Section 4, "Pin Assignments and Reset States," for package diagrams. For a more detailed discussion of the MCF5227x signals, consult the MCF52277 Reference Manual (MCF52277RM).
NOTE
In this table and throughout this document a single signal within a group is designated without square brackets (i.e., FB_A23), while designations for multiple signals within a group use brackets (i.e., FB_A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that are muxed with GPIO will default to their GPIO functionality. See Table 5 for a list of the exceptions. Table 5. Special-Case Default Signal Functionality
Pin FB_BE/BWE[3:0] FB_CS[3:0] FB_OE FB_TA FB_R/W FB_TS Default Signal FB_BE/BWE[3:0] FB_CS[3:0] FB_OE FB_TA FB_R/W FB_TS
Table 6. MCF5227x Signal Information and Muxing
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52274 176 LQFP
MCF52277 196 MAPBGA
Reset RESET RSTOUT -- -- -- -- -- -- Clock EXTAL XTAL -- -- -- -- -- -- Mode Selection BOOTMOD[1:0] -- -- -- --
I EVDD 110, 109 G10, H10
U --
I O
EVDD EVDD
103 102
J11 K11
-- U3
I O
EVDD EVDD
106 105
F14 G14
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52274 176 LQFP
MCF52277 196 MAPBGA
FlexBus FB_A[23:22] FB_A[21:16] FB_A[15:14] FB_A[13:11] FB_A10 FB_A[9:0] -- -- -- -- -- -- FB_CS[5:4] -- SD_BA[1:0] SD_A[13:11] -- SD_A[9:0] -- -- -- -- -- -- -- -- -- --
O O O O O O SDVDD 143, 142 C11, D11 A12, B12, C12, B13, A13, A14 B14, C13 C14, D12, D13 D14 E11-E14, F11-F13, G11, G12, H11 J4, K1-K4, L1-L3, M3, N3, P3,M4, N4, P4, L5, M5 G1-G4, H1-H4, M6, N6, P6, L7, M7, N7, P7, L8 P1 J3, N5, J1, L6 B11, A11 D10 C10 N8 H12 M8 F4
SDVDD 141-139, 137-135 SDVDD SDVDD SDVDD SDVDD 131, 130 129-127 126 125-116
FB_D[31:16]
--
SD_D[31:16]
--
I/O
SDVDD
30-37, 49-56
FB_D[15:0]
--
FB_D[31:16]
--
I/O
SDVDD
19-26, 60-67
FB_CLK FB_BE/BWE[3:0] FB_CS[3:2] FB_CS1 FB_CS0 FB_OE FB_TA FB_R/W FB_TS
-- PBE[3:0] PCS[3:2] PCS1 PCS0 PFBCTL3 PFBCTL2 PFBCTL1 PFBCTL0
-- SD_DQM[3:0] -- SD_CS1 -- -- -- -- DACK0
-- -- -- -- -- -- -- -- -- SDRAM Controller -- -- -- -- -- U -- --
O O O O O O I O O
SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD
42 29, 57, 27, 59
--
144 145 69 115 68 15
SD_A10 SD_CAS SD_CKE SD_CLK SD_CLK SD_CS0 SD_DQS[3:2] SD_RAS SD_SDR_DQS
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
O O O O O O I/O O O
SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD SDVDD
46 47 17 40 41 18 28, 58 48 38
L4 N2 F2 M1 N1 F1 J2, P5 P2 M2
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52274 176 LQFP
MCF52277 196 MAPBGA
SD_WE
--
--
-- External Interrupts Port4
--
O
SDVDD
16
F3
IRQ7 IRQ4 IRQ1
PIRQ7 PIRQ4 PIRQ1
-- DREQ0 USB_CLKIN
-- DSPI_PCS4 SSI_CLKIN LCD Controller6
--
5
I I I
EVDD EVDD EVDD
162 161 160
D7 C7 B7
--
LCD_D[17:16]6 LCD_D[15:14]6 LCD_D13 LCD_D12 LCD_D[11:8]6 LCD_D7 LCD_D6 LCD_D[5:2]6 LCD_D1 LCD_D0 LCD_ACD/ LCD_OE LCD_FLM/ LCD_VSYNC LCD_LP/ LCD_HSYNC LCD_LSCLK
PLCDDH[1:0] PLCDDM[7:6] PLCDDM5 PLCDDM4 PLCDDM[3:0] PLCDDL7 PLCDDL6 PLCDDL[5:2] PLCDDL1 PLCDDL0 PLCDCTL3 PLCDCTL2 PLCDCTL1 PLCDCTL0
LCD_D[11:10] LCD_D[9:8] CANTX CANRX LCD_D[7:4] PWM7 PWM5 LCD_D[3:0] PWM3 PWM1 LCD_SPL_SPR -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- USB On-the-Go
-- -- -- -- -- -- -- -- -- -- -- -- -- --
O O O O O O O O O O O O O O
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
9, 8 7, 6 -- -- 5-2 -- -- 175-172 -- -- 169
E3, E4 D1, D2 C1 C2 D3, C3, D4, B1 B2 A1 A2, A3, B3, A4 B4 C4 B5
EVDD
10
E2
EVDD
11
E1
EVDD
170
A5
USB_DM USB_DP
-- --
-- --
-- -- Real Time Clock
-- --
O O
USB VDD USB VDD
149 150
A9 A10
RTC_EXTAL RTC_XTAL
-- --
-- --
-- --
-- --
I O
EVDD EVDD
100 99
J14 K14
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52274 176 LQFP
MCF52277 196 MAPBGA
ADC ADC_IN[7:0] -- -- -- --
I VDD_ ADC VDD_ ADC 82-85, 87-90 P12, N12, P13, N13, P14, N14, M13, M14 M12
ADC_REF
--
-- I2C
--
--
I
86
I2C_SCL I2C_SDA
PI2C1 PI2C0
CANTX CANRX
U2TXD U2RXD DSPI7
U U
I/O I/O
EVDD EVDD
168 167
C5 D5
DSPI_PCS0/SS DSPI_SIN DSPI_SOUT DSPI_SCK
PDSPI3 PDSPI2 PDSPI1 PDSPI0
U2RTS U2RXD U2TXD U2CTS
-- SBF_DI SBF_D0 SBF_CK UARTs
U
8
I/O I O I/O
EVDD EVDD EVDD EVDD
152 155 154 153
B9 D8 D9 C9
-- --
U1CTS U1RTS U1RXD U1TXD U0CTS U0RTS U0RXD U0TXD
PUART7 PUART6 PUART5 PUART4 PUART3 PUART2 PUART1 PUART0
SSI_BCLK SSI_FS SSI_RXD SSI_TXD DT1OUT DT1IN CANRX CANTX
LCD_CLS LCD_PS -- -- USB_VBUS_EN USB_VBUS_OC -- -- DMA Timers
-- -- -- -- -- -- -- --
I O I O I O I O
EVDD EVDD EVDD EVDD EVDD EVDD EVDD EVDD
156 157 158 159 97 98 96 95
C8 B8 A8 A7 K12 J12 K13 L12
DT3IN DT2IN/SBF_CS DT1IN DT0IN
7
PTIMER3 PTIMER2 PTIMER1 PTIMER0
DT3OUT DT2OUT DT1OUT DT0OUT
SSI_MCLK DSPI_PCS2 LCD_CONTRAST LCD_REV BDM/JTAG9
-- -- -- --
I I I I
EVDD EVDD EVDD EVDD
163 164 165 166
D6 C6 B6 A6
PST[3:0] DDATA[3:0] ALLPST
-- -- --
-- -- --
-- -- --
-- -- --
O O O
EVDD EVDD EVDD
-- -- 76
L9, M9, N9, P9 L10, M10, N10, P10 --
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
Voltage Domain Pull-up (U)1 Pull-down (D) Direction2
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52274 176 LQFP
MCF52277 196 MAPBGA
JTAG_EN PSTCLK DSI DSO BKPT DSCLK
-- -- -- -- -- --
-- TCLK TDI TDO TMS TRST Test
-- -- -- -- -- --
D U U -- U U
I O I O I I
EVDD EVDD EVDD EVDD EVDD EVDD
79 74 78 81 80 77
K10 P8 M11 L11 N11 P11
TEST
--
--
-- Power Supplies
D
I
EVDD
134
E10
IVDD EVDD SD_VDD VDD_OSC VDD_PLL VDD_USB VDD_RTC VDD_ADC VSS VSS_OSC VSS_ADC
1 2 3 4 5 6 7 8 9
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
39, 75, 114, 138, 171
K5, F10, E5, J10
12, 72, 73, 94, 111, E6, E7, F5, F6, G5, 148, 176 H9, J9, K8, K9 14, 43, 44, 70, 113, E8, E9, F9, G9, H5, 132, 146 J5, J6, K6, K7 108 104 151 101 91 1, 13, 45, 71, 93, 112, 133, 147 107 92 G13 H14 B10 J13 L13 F7, F8, G6-G8, H6-H8, J7, J8 H13 L14
Pull-ups are generally only enabled on pins with their primary function, except as noted. Refers to pin's primary function. Enabled only in oscillator bypass mode (internal crystal oscillator is disabled). GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions. Pull-up when DREQ controls the pin. The 176 LQFP device only supports a 12-bit LCD data bus. DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the pins are configured for DSPI. Pull-up when the serial boot facility (SBF) controls the pin. If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Pin Assignments and Reset States
4.2
Pinout--176 LQFP
EVDD LCD_D5 LCD_D4 LCD_D3 LCD_D2 IVDD LCD_LSCLK LCD_ACD/OE I2C_SCL I2C_SDA T0IN T1IN T2IN T3IN IRQ7 IRQ4 IRQ1 U1TXD U1RXD U1RTS U1CTS DSPI_SIN DSPI_SOUT DSPI_SCK DSPI_PCS0 VDD_USB USB_DP USB_DM EVDD VSS SD_VDD FB_CS0 FB_CS1 FB_A23 FB_A22 FB_A21 FB_A20 FB_A19 IVDD FB_A18 FB_A17 FB_A16 TEST VSS
The pinout for the MCF52274 package is shown below.
VSS LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_FLM/VSYNC LCD_LP/HSYNC EVDD VSS SD_VDD FB_TS SD_WE SD_CKE SD_CS0 FB_D15 FB_D14 FB_D13 FB_D12 FB_D11 FB_D10 FB_D9 FB_D8 FB_BE/BWE1 SD_DQS3 FB_BE/BWE3 FB_D31 FB_D30 FB_D29 FB_D28 FB_D27 FB_D26 FB_D25 FB_D24 SD_SDR_DQS IVDD SD_CLK SD_CLK FB_CLK SD_VDD SD_VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
*
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
SD_VDD FB_A15 FB_A14 FB_A13 FB_A12 FB_A11 FB_A10 FB_A9 FB_A8 FB_A7 FB_A6 FB_A5 FB_A4 FB_A3 FB_A2 FB_A1 FB_A0 FB_TA IVDD SD_VDD VSS EVDD BOOTMOD1 BOOTMOD0 VDD_OSC VSS_OSC EXTAL XTAL VDD_PLL RESET RSTOUT VDD_RTC RTC_EXTAL RTC_XTAL U0RTS U0CTS U0RXD U0TXD EVDD VSS VSS_ADC VDD_ADC ADC_IN0 ADC_IN1
14
VSS SD_A10 SD_CAS SD_RAS FB_D23 FB_D22 FB_D21 FB_D20 FB_D19 FB_D18 FB_D17 FB_D16 FB_BE/BWE2 SD_DQS2 FB_BE/BWE0 FB_D7 FB_D6 FB_D5 FB_D4 FB_D3 FB_D2 FB_D1 FB_D0 FB_R/W FB_OE SD_VDD VSS EVDD EVDD PSTCLK IVDD ALLPST DSCLK DSI JTAG_EN BKPT DSO ADC_IN7 ADC_IN6 ADC_IN5 ADC_IN4 ADC_REF ADC_IN3 ADC_IN2
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Figure 7. MCF52274 Pinout (176 LQFP)
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
4.3
1 A LCD_D6
Pinout--196 MAPBGA
2 LCD_D5 3 LCD_D4 4 LCD_D2 5 LCD_ LSCLK LCD_ ACD/OE 6 T0IN 7 U1TXD 8 U1RXD 9 USB_DM 10 USB_DP 11 FB_CS2 12 FB_A21 13 FB_A17 14 FB_A16 A
The pinout for the MCF52277 package is shown below.
B
LCD_D8
LCD_D7
LCD_D3
LCD_D1
T1IN
IRQ_1
U1RTS
DSPI_ PCS0 DSPI_ SCK DSPI_ SOUT
VDD_ USB
FB_CS3
FB_A20
FB_A18
FB_A15
B
C
LCD_D13 LCD_D12 LCD_D10
LCD_D0
I2C_SCL
T2IN
IRQ_4
U1CTS
FB_CS0
FB_A23
FB_A19
FB_A14
FB_A13
C
D
LCD_D15 LCD_D14 LCD_D11
LCD_D9
I2C_SDA
T3IN
IRQ_7
DSPI_SIN
FB_CS1
FB_A22
FB_A12
FB_A11
FB_A10
D
E
LCD_LP/ LCD_FLM/ LCD_D17 LCD_D16 HSYNC VSYNC
IVDD
EVDD
EVDD
SDVDD
SDVDD
TEST
FB_A9
FB_A8
FB_A7
FB_A6
E
F
SD_CS0
SD_CKE
SD_WE
FB_TS
EVDD
EVDD
VSS
VSS
SDVDD
IVDD
FB_A5
FB_A4
FB_A3
EXTAL
F
G
FB_D15
FB_D14
FB_D13
FB_D12
EVDD
VSS
VSS
VSS
SDVDD
BOOT MOD1 BOOT MOD0
FB_A2
FB_A1
VDD_ OSC VSS_ OSC VDD_ RTC
XTAL
G
H
FB_D11
FB_D10
FB_D9
FB_D8
SDVDD
VSS
VSS
VSS
EVDD
FB_A0
FB_TA
VDD_ PLL RTC_ EXTAL RTC_ XTAL VSS_ ADC
H
J
FB_BE/ BWE1
SD_DQS3
FB_BE/ BWE3
FB_D31
SDVDD
SDVDD
VSS
VSS
EVDD
IVDD
RESET
U0RTS
J
K
FB_D30
FB_D29
FB_D28
FB_D27
IVDD
SDVDD
SDVDD
EVDD
EVDD
JTAG_EN RSTOUT
U0CTS
U0RXD
K
L
FB_D26
FB_D25
FB_D24
SD_A10
FB_D17
FB_BE/ BWE0
FB_D4
FB_D0
PST3
DDATA3
TDO
U0TXD
VDD_ ADC
L
M
SD_CLK
SD_ SDR_DQS
FB_D23
FB_D20
FB_D16
FB_D7
FB_D3
FB_R/W
PST2
DDATA2
TDI
ADC_ REF
ADC_IN1 ADC_IN0
M
N
SD_CLK
SD_CAS
FB_D22
FB_D19
FB_BE/ BWE2 SD_ DQS0 5
FB_D6
FB_D2
FB_OE
PST1
DDATA1
TMS
ADC_IN6 ADC_IN4 ADC_IN2
N
P
FB_CLK 1
SD_RAS 2
FB_D21 3
FB_D18 4
FB_D5 6
FB_D1 7
TCLK 8
PST0 9
DDATA0 10
TRST 11
ADC_IN7 ADC_IN5 ADC_IN3 12 13 14
P
Figure 8. MCF52277 Pinout (196 MAPBGA)
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5227x microprocessor. This section contains detailed information on DC/AC electrical characteristics and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
Electrical Characteristics
NOTE
The parameters specified in this MCU document supersede any values found in the module specifications.
5.1
Maximum Ratings
Table 7. Absolute Maximum Ratings1, 2
Characteristic Core Supply Voltage CMOS Pad Supply Voltage DDR/Memory Pad Supply Voltage PLL Supply Voltage Digital Input Voltage
3
Symbol IVDD EVDD SDVDD PLLVDD VIN ID TA (TL - TH) Tstg
Value -0.5 to +2.0 -0.3 to +4.0 -0.3 to +4.0 -0.3 to +2.0 -0.3 to +3.6 25 -40 to +85 -55 to +150
Unit V V V V V mA C C
Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range
1
2
3 4 5
Functional operating conditions are given in Section 5.4, "DC Electrical Specifications." Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or EVDD). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and EVDD. Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of EVDD and could result in external power supply going out of regulation. Insure external EVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum current conditions.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
5.2
Thermal Characteristics
Table 8. Thermal Characteristics
Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
1
Symbol Four layer board (2s2p) Four layer board (2s2p) JMA JMA JB JC jt Tj
196 MAPBGA 471,2 431,2 363 224 6
1,5
176 LQFP TBD TBD TBD TBD TBD TBD
Unit C/W C/W C/W C/W C/W
oC
105
2 3 4 5
JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA )
Eqn. 1
Where:
TA QJMA PD PINT PI/O = = = = = Ambient Temperature, C Package Thermal Resistance, Junction-to-Ambient, C/W PINT + PI/O IDD x IVDD, Watts - Chip Internal Power Power Dissipation on Input and Output Pins -- User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K P D = -------------------------------( T J + 273C )
Eqn. 2
Solving equations 1 and 2 for K gives: K = P D x ( T A x 273C ) + Q JMA x P D
2
Eqn. 3
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
5.3
ESD Protection
Table 9. ESD Protection Characteristics1,2
Characteristic ESD Target for Human Body Model
1
Symbol HBM
Value 2000
Unit V
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 10. DC Electrical Specifications
Characteristic Symbol IVDD PLLVDD EVDD SDVDD 1.7 2.25 3.0 USBVDD EVIH EVIL EVOH EVOL SDVIH 1.35 1.7 2 SDVIL VSS - 0.3 VSS - 0.3 VSS - 0.3 0.45 0.8 0.8 SDVDD + 0.3 SDVDD + 0.3 SDVDD + 0.3 V 3.0 2 VSS - 0.3 EVDD - 0.4 -- 1.95 2.75 3.6 3.6 EVDD + 0.3 0.8 -- 0.4 V V V V V V Min 1.4 1.4 3.0 Max 1.6 1.6 3.6 Unit V V V V
Core Supply Voltage PLL Supply Voltage CMOS Pad Supply Voltage SDRAM and FlexBus Supply Voltage Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) USB Supply Voltage CMOS Input High Voltage CMOS Input Low Voltage CMOS Output High Voltage IOH = -5.0 mA CMOS Output Low Voltage IOL = 5.0 mA SDRAM and FlexBus Input High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) SDRAM and FlexBus Input Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V)
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 10. DC Electrical Specifications (continued)
Characteristic SDRAM and FlexBus Output High Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOH = -5.0 mA for all modes SDRAM and FlexBus Output Low Voltage Mobile DDR/Bus Input High Voltage (nominal 1.8V) DDR/Bus Pad Supply Voltage (nominal 2.5V) SDR/Bus Pad Supply Voltage (nominal 3.3V) IOL = 5.0 mA for all modes Input Leakage Current Vin = VDD or VSS, Input-only pins Weak Internal Pull-Up Device Current, tested at VIL Max.1 Input Capacitance 2 All input-only pins All input/output (three-state) pins
1 2
Symbol SDVOH
Min 1.4 2.1 2.4
Max -- -- --
Unit V
SDVOL -- -- -- Iin IAPU Cin -- -- 7 7 -1.0 -10 0.3 0.3 0.5 1.0 -130
V
A A pF
Refer to the signals section for pins having weak internal pull-up devices. This parameter is characterized before qualification rather than 100% tested.
5.5
Oscillator and PLL Electrical Characteristics
Table 11. PLL Electrical Characteristics
Num 1
Characteristic PLL Reference Frequency Range Crystal reference External reference Core/system frequency CLKOUT Frequency Crystal Start-up Time1,2 EXTAL Input High Voltage Crystal Mode3 All other modes (External, Limp) EXTAL Input Low Voltage Crystal Mode3 All other modes (External, Limp) PLL Lock Time 1,4 Duty cycle of reference XTAL Current Total on-chip stray capacitance on XTAL Total on-chip stray capacitance on EXTAL Crystal capacitive load
1
Symbol fref_crystal fref_ext fsys fsys/2 tcst VIHEXT VIHEXT VILEXT VILEXT tlpll tdc IXTAL CS_XTAL CS_EXTAL CL
Min 16 16 TBD TBD -- VXTAL + 0.4 EVDD/2 + 0.4 -- -- -- 40 1
Max 66.67 66.67 166.67 83.33 10 -- -- VXTAL - 0.4 EVDD/2 - 0.4 50000 60 3 1.5 1.5
Unit MHz MHz MHz MHz ms V V V V CLKIN % mA pF pF
2 3 4
5
7 8 9 10 11 12
See crystal spec
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Electrical Characteristics
Table 11. PLL Electrical Characteristics (continued)
Num 13 Characteristic Discrete load capacitance for XTAL Discrete load capacitance for EXTAL Symbol CL_XTAL CL_EXTAL Min -- Max 2 x (CL - CS_XTAL - CS_EXTAL - CS_PCB)5 4.0 2.0 10 TBD 540 Unit pF
14 15 17
Frequency un-LOCK Range Frequency LOCK Range CLKOUT period jitter measured at fsys max Peak-to-peak jitter (Clock edge to clock edge) Long-term jitter VCO frequency (fvco = fref x PFDR)
2, 3, 6
fUL fLCK Cjitter
-4.0 -2.0 -- --
% fsys % fsys % fsys/2 % fsys/2 MHz
19
1 2 3 4 5 6
fvco
350
This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock reference only. Proper PC board layout procedures must be followed to achieve specifications. This parameter is guaranteed by design rather than 100% tested. This specification is the PLL lock time only and does not include oscillator start-up time.. CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval.
5.6
ASP Electrical Characteristics
Table 12. ASP Electrical Characteristics
Characteristic ASP Analog Supply Voltage Input Voltage Range Internal Reference Voltage Operating Current Consumption Power-down Current Consumption Resolution Sampling rate Integral Non-linearity Differential Non-linearity ADC Internal Clock Frequency Conversion Range Conversion Time Sample Time INL DNL tAIC RAD tADC tADS Symbol VDDA VADIN VREF IDDA_ON IDDA_OFF RES Min 3.0 0 TBD TBD TBD -- -- TBD TBD 2 0 15 3 Max 3.6 VDDA 700 700 1 12 125 TBD TBD 8 VDDA 32 20 Unit V V V uA uA bits KS/s lsb1 lsb1 MHz V tAIC cycles tAIC cycles
Table 12 lists the electrical specifications for the ASP module.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 12. ASP Electrical Characteristics (continued)
Characteristic Multiplexer Settling Time Gain Error Offset Error Input Capacitance Input Leakage Current Input Current (Touchscreen enable)
1
Symbol tAMS GE OE CAIN IALEAK IIN_TS_E
Min
Max 3
Unit tAIC cycles lsb1 lsb1 pF uA uA
-4 -2
4 2 34
lsb: least significant bit
5.6.1
Gain Calculations
Sample
The ideal mapping of input voltage to output digital sample is defined as follows:
4095 SMAX
G0
0
2480
3300
Vi
Figure 9. Gain Calculations In general, the mapping function is: S=G*V Where V is input, S is output, and G is the slope. Nominal Gain G0 = 4095/3300 = 1.24mV-1 Eqn. 5 Eqn. 4
5.7
5.7.1
External Interface Timing Specifications
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21
Electrical Characteristics
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the Flexbus output clock, FB_CLK. All other timing relationships can be derived from these values. Table 13. FlexBus AC Timing Specifications
Num Frequency of Operation FB1 FB2 FB3 FB4 FB5 FB6 FB7
1
Characteristic
Symbol
Min --
Max 83.33 -- 7.0 -- -- -- -- --
Unit MHz ns ns ns ns ns ns ns
Notes fsys/2 tcyc
1
Clock Period (FB_CLK) Address, Data, and Control Output Valid (FB_A[23:0], FB_D[31:0], FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0] and FB_OE) Address, Data, and Control Output Hold (FB_A[23:0], FB_D[31:0], FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0], and FB_OE) Data Input Setup Data Input Hold Transfer Acknowledge (TA) Input Setup Transfer Acknowledge (TA) Input Hold
tFBCK tFBCHDCV tFBCHDCI tDVFBCH tDIFBCH tCVFBCH tCIFBCH
12.0 -- 1 3.5 0 4 0
1, 2
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2.2, "DDR SDRAM AC Timing Specifications," for SD_CS[3:0] timing. 2 The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial. The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read and write bus cycles the address signals are indeterminate.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[23:0] FB2 ADDR[31:X] DATA FB4 FB5
FB_A[23:0] FB_D[31:X]
FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn
FB6 FB7
FB_TA
Figure 10. FlexBus Read Timing
S0 S1 S2 S3
FB_CLK
FB1 FB3 ADDR[23:0] FB2
FB_A[23:0]
FB_D[31:X] FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA
ADDR[31:X]
DATA
FB6 FB7
Figure 11. Flexbus Write Timing
5.7.2
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.2.1
SDR SDRAM AC Timing Specifications
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device's SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
Electrical Characteristics
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS signal and its usage. Table 14. SDR Timing Specifications
Num Characteristic Frequency of Operation SD1 Clock Period SD2 Pulse Width High SD3 Pulse Width Low SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold SD6 SD_SDR_DQS Output Valid SD7 SD_DQS[3:2] input setup relative to SD_CLK SD8 SD_DQS[3:2] input hold relative to SD_CLK SD9 Data (D[31:0]) Input Setup relative to SD_CLK (reference only) SD10 Data Input Hold relative to SD_CLK (reference only) SD11 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid SD12 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
1 2 3 4
Symbol
Min TBD
Max 83.33 TBD 0.55 0.55 0.5 x SD_CLK + 1.0 -- Self timed 0.40 x SD_CLK
Unit MHz ns SD_CLK SD_CLK ns ns ns ns
Notes
1 2 3 3
tSDCK tSDCKH tSDCKH tSDCHACV tSDCHACI tDQSOV tDQVSDCH tDQISDCH tDVSDCH tDISDCH tSDCHDMV tSDCHDMI
12.0 0.45 0.45 -- 2.0 -- 0.25 x SD_CLK
4 5
Does not apply. 0.5xSD_CLK fixed width. 0.25 x SD_CLK 1.0 -- 1.5 -- -- 0.5 x SD_CLK +2 -- ns ns ns ns
6
7
5
6 7
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock. Please see the PLL chapter of the device reference manual for more information on setting the SDRAM clock rate. SD_CLK is one SDRAM clock in ns. Pulse width high plus pulse width low cannot exceed min and max clock period. SD_SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SD_SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat. SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat. The SD_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. Since a read cycle in SDR mode still uses the DQS circuit within the device, it is critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is provided as guidance.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
SD1 SD_CLK
SD2
SD3 SD5 SD_CSn SD_RAS SD_CAS SD_WE A[23:0] SD_BA[1:0]
CMD
SD4
ROW COL
SD11 SDDM SD12 D[31:0]
WD1 WD2 WD3 WD4
Figure 12. SDR Write Timing
SD1 SD_CLK SD_CSn, SD_RAS, SD_CAS, SD_WE A[23:0], SD_BA[1:0] SD5 SD3 SD2
CMD
SD4
3/4 MCLK Reference
ROW
COL
tDQS
SDDM SD6 SD_SDR_DQS
(Measured at Output Pin) Board Delay
SD8
SD_DQS[3:2]
(Measured at Input Pin) Board Delay
SD7
Delayed SD_CLK SD9 D[31:0] from Memories
WD1 WD2 WD3 WD4
NOTE: Data driven from memories relative to delayed memory clock.
SD10
Figure 13. SDR Read Timing
5.7.2.2
DDR SDRAM AC Timing Specifications
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Electrical Characteristics
Table 15. DDR Timing Specifications
Num Characteristic Frequency of Operation DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 Clock Period Pulse Width High Pulse Width Low Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Valid Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold Write Command to first DQS Latching Transition Data and Data Mask Output Setup (DQDQS) Relative to DQS (DDR Write Mode) Data and Data Mask Output Hold (DQSDQ) Relative to DQS (DDR Write Mode) Input Data Skew Relative to DQS (Input Setup) Symbol tDDCK tDDSK tDDCKH tDDCKL tSDCHACV tSDCHACI tCMDVDQ tDQDMV tDQDMI tDVDQ tDIDQ Min TBD 12.0 0.45 0.45 -- 2.0 -- 1.5 1.0 -- 0.25 x SD_CLK + 0.5ns 0.5 Max 83.33 TBD 0.55 0.55 0.5 x SD_CLK + 1.0 -- 1.25 -- -- 1 -- -- Unit MHz ns SD_CLK SD_CLK ns ns SD_CLK ns ns ns ns ns
5 6 7
Notes
1 2 3 3 4
8 9
DD10 Input Data Hold Relative to DQS
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
1 2 3 4 5
6 7
8
9
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same frequency as the internal bus clock. SD_CLK is one SDRAM clock in ns. Pulse-width high plus pulse-width low cannot exceed minimum or maximum clock period. Command output valid should be one-half the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and voltage variations. This specification relates to the required input setup time of today's DDR memories. The device's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0]. The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats will be valid for each subsequent DQS edge. This specification relates to the required hold time of today's DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0]. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system-level board skew (due to routing or other factors). Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn, SD_WE, SD_RAS, SD_CAS
CMD
DD4 A[13:0]
ROW COL
DD11 SD_DQS[3:2] DD6 SD_DM[3:2] DD7
D[31:16]
WD1
WD2
WD3
WD4
DD8
Figure 14. DDR Write Timing
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Electrical Characteristics
DD1 SD_CLK
DD2
DD3 SD_CLK
DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS DD4 A[13:0]
ROW COL CMD
CL=2
CL=2.5
DD9 SD_DQS3/SD_DQS2 CL = 2
DQS Read Preamble
DQS Read Postamble
DD10 D[31:24]/D[23:16]
WD1 DQS Read Preamble WD2 WD3 WD4 DQS Read Postamble
SD_DQS3/SD_DQS2 CL = 2.5
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 15. DDR Read Timing Table 16. DDR Clock Crossover Specifications
Symbol VMP VOUT VID VIX
1
Characteristic Clock output mid-point voltage Clock output voltage level Clock output differential voltage (peak to peak swing) Clock crossing point voltage1
Min 1.05 -0.3 0.7 1.05
Max 1.45 SD_VDD + 0.3 SD_VDD + 0.6 1.45
Unit V V V V
The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0] and SDCLK[1:0] signals.
SD_CLK VIX VMP VIX SD_CLK VID
Figure 16. SD_CLK and SD_CLK Crossover Timing
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
5.8
Num G1 G2 G3 G4
1
General Purpose I/O Timing
Table 17. GPIO Timing1
Characteristic FB_CLK High to GPIO Output Valid FB_CLK High to GPIO Output Invalid GPIO Input Valid to FB_CLK High FB_CLK High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
These general purpose specifications apply to the following signals: IRQn, all UART signals, FlexCAN signals, PWM signals, DACKn and DREQn, and all signals configured as GPIO.
FB_CLK
G1 G2
GPIO Outputs
G3 G4
GPIO Inputs
Figure 17. GPIO Timing
5.9
Num R1 R2 R3 R4 R5 R6 R7 R8
1
Reset and Configuration Override Timing
Table 18. Reset and Configuration Override Timing
Characteristic RESET Input valid to FB_CLK High FB_CLK High to RESET Input invalid RESET Input valid Time
1
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1
Unit ns ns tCYC ns ns tCYC ns tCYC
FB_CLK High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Electrical Characteristics
FB_CLK
R1 R3
RESET
R2
R4
RSTOUT
R4 R8 R5 R6 R7
Configuration Overrides*: (RCON, Override pins)
Figure 18. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF52277 Reference Manual for more information.
5.10
LCD Controller Timing Specifications
Table 19. LCD_LSCLK Timing
Num T1 T2 T3 LCD_LSCLK Period Pixel data setup time Pixel data up time Characteristic Min 25 11 11 Max 2000 -- -- Unit ns ns ns
This sections lists the timing specifications for the LCD Controller.
Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT, or monochrome mode with bus width = 1, LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and LCD_D signals can also be programmed.
T1 LCD_LSCLK
LCD_D[17:0] T2 T3
Figure 19. LCD_LSCLK to LCD_D[17:0] timing diagram
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Non-display Region
T1 T3
Display Region T4
LCD_VSYNC LCD_HSYNC LCD_OE LCD_D[17:0]
T2
Line Y
Line 1
Line Y
T5 LCD_HSYNC LCD_LSCLK LCD_OE LCD_D[15:0]
T6
XMAX
T7
(1,1)
(1,2)
(1,X)
Figure 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Num T1 T2 T3 T4 T5 T6 T7 Characteristic End of LCD_OE to beginning of LCD_VSYNC LCD_HSYNC period LCD_VSYNC pulse width End of LCD_VSYNC to beginning of LCD_OE LCD_HSYNC pulse width End of LCD_HSYNC to beginning to LCD_OE End of LCD_OE to beginning of LCD_HSYNC Min T5 + T6 + T7 - 1 -- T2 1 1 3 1 Value (VWAIT1 x T2) + T5 + T6 + T7 - 1 XMAX+T5+T6+T7 VWIDTH x T2 (VWAIT2 x T2)+1 HWIDTH + 1 HWAIT2 + 3 HWAIT1 + 1 Unit Ts Ts Ts Ts Ts Ts Ts
Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC, and LCD_OE can be programmed as active high or active low. In Figure 20, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 20, LCD_LSCLK is always active. Note: XMAX is defined in number of pixels in one line.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31
Electrical Characteristics
XMAX
LCD_LSCLK
LCD_D
D320
D1
D2
D320
T1 LCD_SPL_SPR T2 LCD_HSYNC T4 LCD_CLS T4 T3 T2
LCD_PS T7 LCD_REV
T5
T6 T7
Figure 21. Sharp TFT Panel Timing Table 21. Sharp TFT Panel Timing
Num T1 T2 T3 T4 T5 T6 T7 Characteristic LCD_SPL/LCD_SPR pulse width End of LCD_D of line to beginning of LCD_HSYNC End of LCD_HSYNC to beginning of LCD_D of line LCD_CLS rise delay from end of LCD_D of line LCD_CLS pulse width LCD_PS rise delay from LCD_CLS negation LCD_REV toggle delay from last LCD_D of line Min -- 1 4 3 1 0 1 Value 1 HWAIT1+1 HWAIT2 + 4 CLS_RISE_DELAY+1 CLS_HI_WIDTH+1 PS_RISE_DELAY REV_TOGGLE_DELAY+1 Unit Ts Ts Ts Ts Ts Ts Ts
Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_D of line. Note: Falling of LCD_PS aligns with rising edge of LCD_CLS. Note: LCD_REV toggles in every LCD_HSYN period.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
T1 LCD_VSYNC T2 LCD_HSYNC T3 XMAX T4 T2
T1
LCD_LSCLK Ts LCD_D[15:0]
Figure 22. Non-TFT Mode Panel Timing Table 22. Non-TFT Mode Panel Timing
Num T1 T2 T3 T4 Characteristic LCD_HSYNC to LCD_VSYNC delay LCD_HSYNC pulse width LCD_VSYNC to LCD_LSCLK LCD_LSCLK to LCD_HSYNC Min 2 1 -- 1 Value HWAIT2 + 2 HWIDTH + 1 0 T3 Ts HWAIT1 + 1 Unit Tpix Tpix -- Tpix
Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC, and LCD_LSCLK can be programmed as active high or active low. In Figure 22, all these 3 signals are active high. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width = 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.
5.11
USB On-The-Go Specifications
Table 23. USB On-Chip Transceiver DC Characteristics
Characteristic Input High Input Low Input Differential Differential Common Mode Range Single Ended Receive Threshold Single Ended Receive Hysteresis Output High Output Low Differential Output Crossover Driven Driven DP = DM (DP - DM) Condition Driven Symbol VIH VIL VID VCM VSETHR VSEHYS VOH VOL VCRS Min 2.0 -- 200 0.8 0.8 -- 0.0 2.8 1.3 Typ -- -- -- -- -- 400 -- -- -- Max -- 0.8 00 2.5 2.0 -- 300 2.0 2.0 Unit V V mV V V mV mV V V
The MCF5227x device is compliant with industry standard USB 2.0 specification.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
Electrical Characteristics
Table 23. USB On-Chip Transceiver DC Characteristics (continued)
Characteristic P side Impedance M side Impedance Impedance Matching P/M Pulldown Resistance1
1
Condition Driven Driven
Symbol ZP ZM ZMatching RPD
Min 6.25 6.25 -- 30k
Typ 8.25 8.25 0.17 50k
Max 11.25 11.25 0.23 70k
Unit
The pulldown resistors are included to provide a method to keep DP and DM signals in a known quiescent state if desired when the USB port is not being used or when the USB cable is not connected. These on-chip resistors should not be used to provide the 15-k host-mode pulldowns called for in Chapter 7 of the USB Specification, Rev. 1.1 or Rev. 2.0.
Table 24. USB On-Chip Transceiver Full Speed AC Characteristics
Characteristic Rise Time Fall Time Rise/Fall Matching Rise/Fall Matching, DP and DM TIme Skew Between DP and DM Condition 10-90% 90-10% -- -- -- Symbol tLH tHL t LH ------- Matching t HL t LH ------- Pad-to-Pad t HL tSKE Min 7 7 20 330 100 Typ 11 11 40 360 140 Max 17.5 17.5 60 640 210 Unit ns ns ps ps ps
Table 25. USB On-Chip Transceiver Low Speed AC Characteristics
Characteristic Rise Time Fall Time Rise/Fall Matching Condition 10-90% 90-10% t LH ------t HL Symbol tLH tHL t LH ------- Matching t HL Min 75 75 80 Typ -- -- -- Max 300 300 125 Unit ns ns %
5.12
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync (SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below. Table 26. SSI Timing--Master Modes1
Num S1 S2 S3 S4 Characteristic SSI_MCLK cycle time SSI_MCLK pulse width high / low SSI_BCLK cycle time SSI_BCLK pulse width tBCLK Symbol tMCLK Min 4 x tSYS 45% 4 x tSYS 45% Max -- 55% -- 55% Unit ns tMCLK ns tBCLK
3
Notes
2
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 26. SSI Timing--Master Modes1 (continued)
Num S5 S6 S7 S8 S9 S10
1 2
Characteristic SSI_BCLK to SSI_FS output valid SSI_BCLK to SSI_FS output invalid SSI_BCLK to SSI_TXD valid SSI_BCLK to SSI_TXD invalid / high impedence SSI_RXD / SSI_FS input setup before SSI_BCLK SSI_RXD / SSI_FS input hold after SSI_BCLK
Symbol
Min -- 0 -- 0 10 0
Max 10 -- 10 -- -- --
Unit ns ns ns ns ns ns
Notes
All timings specified with a capactive load of 25pF. SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK). 3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not exceed 4 x fSYS.
Table 27. SSI Timing--Slave Modes1
Num S11 S12 S13 S14 S15 S16 S17 S18
1
Characteristic SSI_BCLK cycle time SSI_BCLK pulse width high / low SSI_FS input setup before SSI_BCLK SSI_FS input hold after SSI_BCLK SSI_BCLK to SSI_TXD / SSI_FS output valid SSI_BCLK to SSI_TXD / SSI_FS output invalid / high impedence SSI_RXD setup before SSI_BCLK SSI_RXD hold after SSI_BCLK
Symbol tBCLK
Min 4 x tSYS 45% 10 2 -- 0 10 2
Max -- 55% -- -- 10 -- -- --
Unit ns tBCLK ns ns ns ns ns ns
Notes
All timings specified with a capactive load of 25 pF.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35
Electrical Characteristics
S1
S2
S2
SSI_MCLK (Output)
S3
SSI_BCLK (Output)
S5
S4
S4 S6
SSI_FS (Output)
S9 S10 S7 S7 S8 S8
SSI_FS (Input)
SSI_TXD
S9 S10
SSI_RXD
Figure 23. SSI Timing--Master Modes
S11
SSI_BCLK (Input)
S15
S12 S12 S16
SSI_FS (Output)
S13
SSI_FS (Input)
S15
S14 S15 S16 S16
SSI_TXD
S17 S18
SSI_RXD
Figure 24. SSI Timing--Slave Modes
5.13
I2C Timing Specifications
Table 28. I2C Input Timing Specifications between SCL and SDA
Num I1 I2 I3 I4 Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time Characteristic Min 2 8 -- 0 Max -- -- 1 -- Unit tcyc tcyc ms ns
Table 28 lists specifications for the I2C input timing parameters shown in Figure 25.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 28. I2C Input Timing Specifications between SCL and SDA (continued)
Num I5 I6 I7 I8 I9 Characteristic I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min -- 4 0 2 2 Max 1 -- -- -- -- Unit ms tcyc ns tcyc tcyc
Table 29 lists specifications for the I2C output timing parameters shown in Figure 25. Table 29. I2C Output Timing Specifications between SCL and SDA
Num I11 I21 I32 I41 I53 I61 I71 I81 I91
1
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 10 -- 7 -- 10 2 20 10
Max -- -- -- -- 3 -- -- -- --
Unit tcyc tcyc s tcyc ns tcyc tcyc tcyc tcyc
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 29. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 29 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 25 shows timing for the values in Table 29 and Table 28.
I5 I2 I2C_SCL I1 I2C_SDA I4 I7 I8 I9 I6
I3
Figure 25. I2C Input/Output Timings
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37
Electrical Characteristics
5.14
DMA Timer Timing Specifications
Table 30. Timer Module AC Timing Specifications
Num T1 T2 Characteristic DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width Min 3 1 Max -- -- Unit tCYC tCYC
Table 30 lists timer module AC timings.
5.15
DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many of the transfer attributes are programmable. Table 31 provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the MCF52277 Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 31. DSPI Module AC Timing Specifications1
Num DS1 DS2 Characteristic DSPI_SCK Cycle Time DSPI_SCK Duty Cycle Symbol tSCK -- Min 4 x tSYS (tsck / 2) - 2.0 Max -- (tsck / 2) + 2.0 Unit ns ns Notes
2
Master Mode DS3 DS4 DS5 DS6 DS7 DS8 DSPI_PCSn to DSPI_SCK delay DSPI_SCK to DSPI_PCSn delay DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold tCSC tASC -- -- -- -- (2 x tSYS) - 2.0 (2 x tSYS) - 3.0 -- -5 9 0 -- -- 5 -- -- -- ns ns ns ns ns ns
3 4
Slave Mode DS9 DS10 DS11 DS12 DS13 DS14
1
DSPI_SCK to DSPI_SOUT valid DSPI_SCK to DSPI_SOUT invalid DSPI_SIN to DSPI_SCK input setup DSPI_SCK to DSPI_SIN input hold DSPI_SS active to DSPI_SOUT driven DSPI_SS inactive to DSPI_SOUT not driven
-- -- -- -- -- --
-- 0 2 7 -- --
4 -- -- -- 20 18
ns ns ns ns ns ns
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges. 2 When in master mode, the baud rate is programmable in DCTARn[PBR] and DCTARn[BR]. 3 The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK]. 4 The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
DS3
DS4
DSPI_PCSn
DS1 DS2
DSPI_SCK (DCTARn[CPOL] = 0)
DS2
DSPI_SCK (DCTARn[CPOL] = 1)
DS7 DS8
DSPI_SIN
First Data DS6
Data
Last Data
DS5 Data Last Data
DSPI_SOUT
First Data
Figure 26. DSPI Classic SPI Timing--Master Mode
DSPI_SS
DS1
DSPI_SCK (DCTARn[CPOL] = 0)
DS2
DS2
DSPI_SCK (DCTARn[CPOL] = 1)
DS13 DS10 First Data DS11 DS12 Data Last Data Data DS9
DS14
DSPI_SOUT
Last Data
DSPI_SIN
First Data
Figure 27. DSPI Classic SPI Timing--Slave Mode
5.16
SBF Timing Specifications
The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 32 provides the AC timing specifications for the SBF.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39
Electrical Characteristics
Table 32. SBF AC Timing Specifications
Num SB1 SB2 SB3 SB4 SB5 SB6 SB7 SB8
1
Characteristic SBF_CK Cycle Time SBF_CK High/Low Time SBF_CS to SBF_CK delay SBF_CK to SBF_CS delay SBF_CK to SBF_DO valid SBF_CK to SBF_DO invalid SBF_DI to SBF_SCK input setup SBF_CK to SBF_DI input hold
Symbol tSBFCK -- -- -- -- -- -- --
Min 30 30% tSBFCK - 2.0 tSBFCK - 2.0 -- 0 6 0
Max -- -- -- -- 12 -- -- --
Unit ns tSBFCK ns ns ns ns ns ns
Notes
1
At reset, the SBF_CK cycle time is tREF x 67. The first byte of data read from the serial memory contains a divider value that is used to set the SBF_CK cycle time for the duration of the serial boot process.
SB1 SB2 SB2 SB4
SBF_CK
SB3
SBF_CS
SB7 SB8 Data Last Data SB5 Data Last Data
SBF_DI
First Data SB6
SBF_DO
First Data
Figure 28. SBF Timing
5.17
Num J1 J2 J3 J4 J5 J6 J7 J8
JTAG and Boundary Scan Timing Specifications
Table 33. JTAG and Boundary Scan Timing
Characteristic1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ Min DC 4 26 0 4 26 0 0 Max 1/4 -- -- 3 -- -- 33 33 Unit fsys/2 tCYC ns ns ns ns ns ns
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 33. JTAG and Boundary Scan Timing (continued)
Num J9 J10 J11 J12 J13 J14
1
Characteristic1 TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High
Symbol tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST
Min 4 10 0 0 100 10
Max -- -- 26 8 -- --
Unit ns ns ns ns ns ns
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2 J3 J3
TCLK (input)
J4
VIH
VIL J4
Figure 29. Test Clock Input Timing
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 30. Boundary Scan (JTAG) Timing
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2008. All rights reserved.
Document Number: MCF52277
Rev. 6 07/2008
Preliminary--Subject to Change Without Notice
Electrical Characteristics
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 31. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 32. TRST Timing
5.18
Debug AC Timing Specifications
Table 34. Debug AC Timing Specification
Num D0 D1 D2 D3 D4
1
Table 34 lists specifications for the debug AC timing parameters shown in Figure 33.
Characteristic PSTCLK cycle time PSTCLK rising to PSTDDATA valid PSTCLK rising to PSTDDATA invalid DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT assertion time
Min 1 -- 1.5 1 4 5 1
Max 1 3.0 -- -- -- -- --
Units tSYS ns ns PSTCLK PSTCLK PSTCLK PSTCLK
D5 D6
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43
Package Information
D0
PSTCLK
D1 D2
PSTDDATA[7:0]
Figure 33. Real-Time Trace AC Timing
D5 DSCLK
D3
DSI
Current D4
Next
DSO
Past
Current
Figure 34. BDM Serial Port AC Timing
6
Package Information
The latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/coldfire. The following table lists the case outline numbers per device. Use these numbers in the web page's keyword search engine to find the latest package outline drawings. Table 35. Package Information
Device MCF52274 MCF52277 Package Type 176 LQFP 196 MAPBGA Case Outline Numbers 98ASS23479W 98ASH98061A
7
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 44 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Revision History
8
f
Revision History
Table 36. MCF52277 Data Sheet Revision History
Rev. No. 3 4 5 6 Date of Release 02/2008 05/2008 07/2008 07/2008 Initial public revision. Corrected MCF52274 order number from MCF52274CAB120 to MCF52274CLU120 in Table 2 Corrected MCF52277CVM166 part number to MCF52277CVM160 in Table 2. Although, this device has a maximum rated frequency of 166.67 MHz. Added data to Section 3.5, "Power Consumption Specifications." Summary of Changes
Table 36 summarizes revisions to this document.
MCF5227x ColdFire(R) Microprocessor Data Sheet, Rev. 6 Freescale Semiconductor Preliminary--Subject to Change Without Notice 45
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2008. All rights reserved.
Document Number: MCF52277
Rev. 6 07/2008
Preliminary--Subject to Change Without Notice

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